View IS34C02B_2420268.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 advanced information rev. 00d 03/21/06 IS34C02B issi ? copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtai n the latest version of this device specification before relying on any published information and before placing orders for products. 2k-bit 2-wire serial cmos eeprom with permanent and reversible write-protection features ? two-wire serial interface, i 2 c tm compatible ? bidirectional data transfer protocol ? 400 khz (2.5v) and 100 khz (1.7v) compat- ibility ? organization: ? 256 x 8-bit ? data protection features ? write protect pin ? permanent software protection ? reversible software protection ? 16-byte page write buffer ? partial page-writes permitted ? low power cmos technology ? active current less than 3 ma (3.6v) ? standby current less than 1 a (1.7v) ? standby current less than 2 a (3.6v) ? low voltage operation ? IS34C02B-2: vcc = 1.7v to 3.6v ? random or sequential read modes ? filtered inputs for noise suppression ? self timed write cycle (5ms max.) ? high reliability ? endurance: 1,000,000 cycles ? data retention: 40 years ? industrial temperature range ? 8-pin tssop and dfn (leadless array) ? lead-free available advanced information april 2006 description the IS34C02B is an electrically erasable prom device that uses the industry-standard i 2 c communication protocol. the IS34C02B contains a non-volatile memory array of 2,048-bits (256k x 8 bytes), and is further subdivided into 16 pages of 16 bytes each for page- write mode. the device operates over the voltage range of 1.7v to 3.6v to satisfy the voltage requirements of ddr2, ddr1, and many other specifications. in normal read or write operations, a master device communi- cates with the eeprom via the two wires serial clock and serial data. during application system boot-up, it may be necessary to read out the contents of the IS34C02B that pertain to the configuration of a dram module. if the module manufacturer wishes to safe- guard this memory content, the first half of the array can be write-protected with either a permanent or reversible software command, or the entire array can be write- protected with the wp input pin. the IS34C02B has three address pins, allowing up to eight devices (or memory modules) to be uniquely accessible in a sys- tem. to minimize board real-estate, IS34C02B is available in two space-saving packages: tssop(8), and dfn(8). all these features make the device ideal for use as a serial presence detect (spd) eeprom in various types of memory modules.
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00d 03/21/06 IS34C02B issi ? functional block diagram > control logic x decoder slave address register & comparator word address counter high voltage generator, timing & control y decoder data register clock di/o ack gnd wp scl sda vcc nmos a0 a1 a2 array 80h-ffh 00h-7fh
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 advanced information rev. 00d 03/21/06 IS34C02B issi ? pin descriptions a0-a2 address inputs sda serial address/data i/o scl serial clock input wp write protect input vcc power supply gnd ground scl this input clock pin is used to synchronize the data transfer to and from the device. sda the sda is a bi-directional pin used to transfer addresses and data into and out of the device. the sda pin is an open drain output and can be wire or'ed with other open drain or open collector outputs. the sda bus requires a pullup resistor to vcc. pin configuration 8-pin tssop wp wp is the write protect pin. if the wp pin is tied to vcc, the entire array becomes write protected, and software write- protection cannot be initiated. when wp is tied to gnd or left floating, normal read/write operations are allowed to the device. if the device has already received a write-protection command, the memory in the range of 00h-7fh is read -only regardless of the setting of the wp pin. a0, a1, a2 the a0, a1, and a2 are the device address inputs that are hardwired or left unconnected for hardware flexibility. when pins are hardwired, as many as eight devices may be addressed on a single bus system. when the pins are not hardwired, the default values of a0, a1, and a2 are zero. device operation the IS34C02B features a serial communication and supports a bi-directional 2-wire bus transmission protocol called i 2 c tm . 2-wire bus the two-wire bus is defined as a serial data line (sda), and a serial clock line (scl). the protocol defines any device that sends data onto the sda bus as a transmitter, and the receiving device as a receiver. the bus is controlled by master device which generates the scl, controls the bus access and generates the stop and start conditions. the IS34C02B is the slave device on the bus. 8-pad dfn 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda (top view)
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00d 03/21/06 IS34C02B issi ? the bus protocol: ? data transfer may be initiated only when the bus is not busy ? during a data transfer, the sda line must remain stable whenever the scl line is high. any changes in the sda line while the scl line is high will be interpreted as a start or stop condition. the state of the sda line represents valid data after a start condition. the sda line must be stable for the duration of the high period of the clock signal. the data on the sda line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. start condition the start condition precedes all commands to the device and is defined as a high to low transition of sda when scl is high. the IS34C02B monitors the sda and scl lines and will not respond until the start condition is met. stop condition the stop condition is defined as a low to high transition of sda when scl is high. all operations must end with a stop condition. acknowledge (ack) after a successful data transfer, each receiving device is required to generate an ack. the acknowledging device pulls down the sda line. reset the IS34C02B contains a reset function in case the 2- wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. the reset is caused when the master device creates a start condition. to do this, it may be necessary for the master device to monitor the sda line while cycling the scl up to nine times. (for each clock signal transition to high, the master checks for a high level on sda.) standby mode power consumption is reduced in standby mode. the IS34C02B will enter standby mode: a) at power-up, and remain in it until scl or sda toggles; b) following the stop signal if no write operation is initiated; or c) following any internal write operation device addressing the master begins a transmission by sending a start condition. the master then sends the address of the particular slave devices it is requesting. the slave device (fig. 5) address is 8 bits. the four most significant bits of the slave device address are fixed as 1010 for normal read/write operations, and 0110 for permanent write-protection operations. this device has three address bits (a1, a2, and a0) that allow up to eight IS34C02B devices to share the 2-wire bus. upon receiving the slave address, the device compares the three address bits with the hardwired a2, a1, and a0 input pins to determine if it is the appropriate slave. if any of the a2 - a0 pins is neither biased to high nor low, internal circuitry defaults the value to low. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master transmits the start condition and slave address byte (fig. 5), the appropriate 2-wire slave (eg. IS34C02B) will respond with ack on the sda line. the slave will pull down the sda on the ninth clock cycle, signaling that it received the eight bits of data. the selected IS34C02B then prepares for a read or write operation by monitoring the bus.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 advanced information rev. 00d 03/21/06 IS34C02B issi ? write operation byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w set to zero) to the slave device. after the slave generates an ack, the master sends a byte address that is written into the address pointer of the IS34C02B. after receiving another ack from the slave, the master device transmits the data byte to be written into the address memory location. the IS34C02B acknowledges once more and the master generates the stop condition, at which time the device begins its internal programming cycle. while this internal cycle is in progress, the device will not respond to any request from the master device. page write the IS34C02B is capable of 16-byte page-write operation. a page-write is initiated in the same manner as a byte write, but instead of terminating the internal write cycle after the first data byte is transferred, the master device can transmit up to 15 more bytes. after the receipt of each dat a byte, the IS34C02B responds immediately with an ack on sda line, and the four l ower order data byte address bits are internally incremented by one, while the higher order bits of the data byte address remain constant. if a byte address is incremented from the last byte of a page, it returns to the first byte of that page. if the m aster device should transmit more than 16 bytes prior to issuing the stop condition, the address counter will ?roll over,? and the previously written data will be overwritten. once all 16 bytes are received and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the IS34C02B in a single write cycle. all inputs are disabled until completion of the internal write cycle. acknowledge (ack) polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host's write operation, the IS34C02B initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the IS34C02B is still busy with the write operation, no no acknowledge (noack) will be returned. if the IS34C02B has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. write protection hardware write protection the IS34C02B has two forms of software write protec- tion and one form of hardware write protection. the hardware write protection is enabled when the wp input is held high. in this case, the entire array of the IS34C02B is read-only regardless of the status of the software protection. the hardware protection is disabled when the wp input is held low or is floating. in this case, the upper half of the array (80h-ffh) can be modified by a valid write command, and the lower half of the array ( 00h-7fh ) can be modified only if software write protection has not been enabled. reversible software write protection there is a non-volatile flag for each of the two forms of software write protection. when the bit value for either flag or both flags is 1, it is not possible to modify the contents of the lower 128 bytes of the array ( 00h-7fh ). if the bit value for both flags is 0, it is possible to modify this half of the array with a valid write command, assuming wp is held low or is floating. the device is shipped with both flags cleared. one of those flags is the reversible software write protection (rswp) flag, and can be changed with the set rswp and clear rswp commands. the flag can also be verified without being changed with a read swp command. in order to set, clear or read the rswp, the IS34C02B input pins must be as follows: a0 must be held to an extra high voltage of vhv (see dc characteristics), while a2 and a1 must be set high, low, or left floating, depending on the desired command (see figure 5). once these input conditions are met, a command can be issued to the device. the reversible software commands are initiated similarly to a normal byte write operation; however, the slave device address begins with the bit values 0110. the next three bits are a2 = 0, a1 = 0 or 1, and a0 = 1, so that they logically match the values on the input pins. if the last bit of the slave device address (r/ w ) is 0, the rswp flag can be cleared or set. if r/ w is 1, the flag can be verified with the read swp command. following this bit, the device responds with either ack or noack, depending on the exact command and the flag status (see table 1: reversible instructions). to complete the
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00d 03/21/06 IS34C02B issi ? set rswp or clear rswp command, the master must transmit a dummy address byte, a dummy data byte, and a stop signal. to actually modify the rswp flag, wp should be held low or be floating during entire command sequence. before resuming any other command, the internal write cycle time should be observed. to complete the read swp status or read cwp status command, the master can transmit a stop signal after the ack/noack. the wp input is not evaluated for the read swp status or read csp status commands. permanent software write protection the IS34C02B contains a permanent software write protection (pswp) feature. if the non-volatile pswp flag has a bit value of 1, the array region of 00h-7fh is protected from modification. if the pswp flag has a bit value of 0, the write protection for the lower half of the array is determined solely by the statuses of rswp and the wp input. after the pswp flag is set to 1 via the permanent write protect command, the protected area becomes irreversibly read-only despite power removal and re-application on the device. once enabled, the permanent protection is independent of the status of the wp pin. the permanent software write protect command is initiated similarly to a normal byte write operation; however, the slave device address begins with the bit values of 0110 (see figure 5). the following three bits are a2-a0 , so that they logically match the values on the input pins . the last bit of the slave address (r/ w ) is 0. the IS34C02B responds with either ack or noack, depending on the flag status (see table 1: permanent instructions). assuming an ack is received, master then must complete the sequence by transmitting a dummy address byte, dummy data byte, and a stop signal (see figure 11). the wp pin should be held low or left floating during the entire command. before resuming any other command, the internal write cycle should be observed. the status of the pswp can be safely determined without any changes by transmitting the same slave address as above, but with the last bit (r/ w ) set to 1 (see figure 12). if the pswp has been set, the IS34C02B will not acknowledge any slave address starting with bits 0110 (see figure 5). to complete the command, the master can transmit a stop signal after the ack/noack.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 advanced information rev. 00d 03/21/06 IS34C02B issi ? table 1 normal instructions command pswp rswp wp 1 ack address ack data byte data byte write (permanen t) (reversible) command address ack cycle read x x x ack 00h-ffh ack d ata byte ack no write 0 0 0 ack 00h-ffh ack d ata byte ack yes write x x 1 ack 00h-ffh ack d ata byte ack no write 1 x x ack 00h-7fh ack d ata byte ack no write x 1 x ack 00h-7fh ack d ata byte ack no write x x 0 ack 80h-ffh ack d ata byte ack yes permanent instructions command pswp rswp wp 1 ack address ack data byte data byte write (permanen t) (reversible) command address ack cycle read pswp status 4 0 x x ack dummy ack dummy ack no address byte read pswp status 1 x x noack ? ? ? ? no set pswp 0 x 0 ack dummy ack dummy ack yes address byte set pswp 1 x 0 noack ? ? ? ? no set pswp 0 x 1 ack dummy ack dummy ack no address byte set pswp 1 x 1 noack ? ? ? ? no reversible instructions command pswp rswp wp 1 ack address ack data byte data byte write (permanen t) (reversible) command address ack cycle read swp status 4 x 0 x ack dummy ack dummy ack no address byte read swp status x 1 x noack ? ? ? ? no read cwp status 3,4 0 x x ack dummy ack dummy ack no address byte read cwp status 3 1 x x noack ? ? ? ? no set rswp x 0 0 ack dummy ack dummy ack yes address byte set rswp x 1 0 noack ? ? ? ? no set rswp x 0 1 ack dummy ack dummy ack no address byte set rswp x 1 1 noack ? ? ? ? no clear rswp 0 x 0 ack dummy ack dummy ack yes address byte clear rswp 1 x 0 noack ? ? ? ? no clear rswp 0 x 1 ack dummy ack dummy ack no address byte clear rswp 1 x 1 noack ? ? ? ? no notes: 1. wp = 1 if input level is high. wp = 0 if input level is gnd or floating. 2. x = don?t care. 3. read cwp status yields the same result as read pswp status. 4. read out don't care dummy address and dummy data is optional.
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00d 03/21/06 IS34C02B issi ? sequential read sequential reads can be initiated as either a current address read or random address read. after the IS34C02B sends the initial byte sequence, the master device responds with an ack indicating it requires additional data from the IS34C02B. the IS34C02B continues to output data for each ack received. the master device terminates the sequential read operation by pulling sda high (no ack) indicating the last data byte to be read, followed by a stop condition. the data output is sequential, with the data from address n followed by the data from address n+1, ... etc. the address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential read operations. when the memory address boundary 255 is reached, the address counter ?rolls over? to address 0, and the IS34C02B continues to output data for each ack received. (refer to figure 10. sequential read operation starting with a random address read diagram.) read operation read operations are initiated in the same manner as write operations, except that the (r/ w ) bit of the slave address is set to ?1?. there are three read operation options: current address read, random address read and sequential read. current address read the IS34C02B contains an internal address counter which maintains the address of the last byte accessed, incremented by one. for example, if the previous operation is either a read or write operation addressed to the address location n, the internal address counter would increment to address location n+1. when the IS34C02B receives the device addressing byte with a read operation (r/ w bit set to ?1?), it will respond an ack and transmit the 8-bit data byte stored at address location n+1. the master should not acknowledge the transfer but should generate a stop condition so the IS34C02B discontinues transmission. if the last byte of the memory was the previous access, the data from location '0' will be transmitted. (refer to figure 8. current address read diagram.) random address read selective read operations allow the master device to select at random any memory location for a read operation. the master device first performs a 'dummy' write operation by sending the start condition, slave address and word address of the location it wishes to read. after the IS34C02B acknowledges the word address, the master device resends the start condition and the slave address, this time with the r/ w bit set to one. the IS34C02B then responds with its ack and sends the data requested. the master device does not send an ack but will generate a stop condition. (refer to figure 9. random address read diagram.)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 advanced information rev. 00d 03/21/06 IS34C02B issi ? scl sda master transmitter/ receiver IS34C02B vcc figure 1. typical system bus configuration t aa data output from transmitter scl from master data output from receiver 189 ack t a a figure 2. output acknowledge stop condition scl sda start condition figure 3. start and stop conditions
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00d 03/21/06 IS34C02B issi ? figure 5. command configuration figure 4. data validity protocol scl sda data stable data stable data change figure 6. byte write sda bus activity s t a r t m s b l s b m s b w r i t e s t o p r/ w a c k a c k a c k data device address word address *** * acknowledges provided by the slave regardless of hardware or software write protection. 7 bit 43 1 2 5 60 r/ w a0 a1 a2 0 1 0 1 normal instruction 2 r/ w a0 a1 a2 0 1 01 permanent write protection instruction 2 pin connection 1 slave device address a2 a2 a1 a0 a2 a1 a0 0 1 0 0 0 1 01 set write protection (swp) gnd gnd v hv 0 1 1 0 0 1 01 clear write protection (cwp) gnd vcc v hv 1 1 0 0 0 1 01 read swp gnd gnd v hv 1 1 1 0 0 1 01 read cwp gnd vcc v hv a1 a0 note: 1. a2-a0 input pin connections must be gnd (or floating), vcc, or v hv . 2. bits 1, 2, and 3 of the device address will be compared with the values on the external pins.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 advanced information rev. 00d 03/21/06 IS34C02B issi ? figure 8. current address read figure 9. random address read sda bus activity s t a r t m s b l s b n o a c k r e a d s t o p a c k data device address r/w sda bus activity a c k a c k a c k data n word address (n) device address dummy write device address s t a r t w r i t e r e a d s t a r t s t o p m s b l s b n o a c k r/w figure 7. page write sda bus activity s t a r t m s b l s b w r i t e a c k a c k a c k a c k data (n+1) data (n) word address (n) device address s t o p a c k data (n+15) r/w ** * * * * acknowledges provided by the slave regardless of hardware or software write protection.
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00d 03/21/06 IS34C02B issi ? figure 11. set permanent write protection figure 12. read permanent write protection sda bus activity s t a r t m s b l s b r e a d a c k device address r/w s t o p * * the slave does not provide an acknowledgement if the permanent write protection is already enabled. sda bus activity s t a r t m s b l s b m s b w r i t e s t o p r/w a c k a c k a c k data device address word address * * the slave does not provide an acknowledgement if the permanent write protection is already enabled. # ### ## ## ######## # don't care bits are required. figure 10. sequential read s t o p n o a c k a c k a c k a c k a c k data byte n+x data byte n+1 data byte n data byte n+2 r/w sda bus activity device address r e a d
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 advanced information rev. 00d 03/21/06 IS34C02B issi ? absolute maximum ratings (1) symbol parameter value unit v s supply voltage ?0.5 to +6.5 v v p voltage on any pin ?0.5 to vcc + 0.5 v t bias temperature under bias ?55 to +125 c t stg storage temperature ?65 to +150 c i out output current 5 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating range (IS34C02B-2) range ambient temperature v cc industrial ?40c to +85c 1.7v to 3.6v capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 400 khz, vcc = 3.0v.
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00d 03/21/06 IS34C02B issi ? dc electrical characteristics industrial (t a = -40 o c to +85 o c) symbol parameter test conditions min. max. unit v ol 1 output low voltage v cc = 1.7v, i ol = 0.15 ma ? 0.2 v v ol 2 output low voltage v cc = 3.6v, i ol = 2.1 ma ? 0.4 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v il input low voltage ?1.0 v cc x 0.3 v v hv a0 high voltage v hv - v cc > 4.8v 7 10 v i li input leakage current v in = v cc max. ? 3 a i lo output leakage current ? 3 a ac electrical characteristics industrial (t a = -40 o c to +85 o c) 1.7v vcc < 2.2v 2.2v vcc 3.6v symbol parameter min. max. min. max. unit f scl scl clock frequency 0 100 0 400 khz t noise suppression time (1) ? 100 ? 50 ns t low clock low period 4.7 ? 1.2 ? s t high clock high period 4 ? 0.6 ? s t buf bus free time before new transmission (1) 4.7 ? 1.2 ? s t su:sta start condition setup time 4 ? 0.6 ? s t su:sto stop condition setup time 4 ? 0.6 ? s t hd:sta start condition hold time 4 ? 0.6 ? s t hd:sto stop condition hold time 4 ? 0.6 ? s t su:dat data in setup time 100 ? 100 ? ns t hd:dat data in hold time 0 ? 0 ? ns t su : wp wp pin setup time 4 ? 0.6 ? s t hd : wp wp pin hold time 4.7 ? 1.2 ? s t dh data out hold time (scl low to sda data out change) 100 ? 50 ? ns t aa clock to output ( scl low to sda data out valid) 100 3500 50 900 ns t r scl and sda rise time (1) ? 1000 ? 300 ns t f scl and sda fall time (1) ? 300 ? 300 ns t wr write cycle time ? 5 ? 5 ms power supply characteristics industrial (t a = -40 o c to +85 o c) symbol parameter test conditions min. max. unit i cc 1 vcc operating current read at 100 khz (vcc = 3.6v) ? 1.0 ma i cc 2 vcc operating current write at 100 khz (vcc = 3.6v) ? 3.0 ma i sb 1 standby current vcc = 1.7v ? 1 a i sb 2 standby current vcc = 3.6v ? 2 a notes: v il min and v ih max are reference only and are not tested. note: 1. these parameters are characterized, but not 100% tested.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 advanced information rev. 00d 03/21/06 IS34C02B issi ? 8th bit ack word n stop condition start condition t wr scl sda figure 14. write cycle timing figure 13. ac waveforms t su:sta t f t high t low t r t su:sto t buf t dh t aa t hd:sta t hd:dat t su:dat scl sda in sda out t su:wp t hd:wp wp
16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advanced information rev. 00d 03/21/06 IS34C02B issi ? ordering information industrial range: -40c to +85c, lead-free voltage range part number package 1.7v IS34C02B-2dli dfn to 3.6v IS34C02B-2zli tssop
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 02/13/06 copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. dual flat no-lead package code: d (8-pad) a2 b (8x) (8x) a1 a1 a3 d e a l (8x) l (8x) e (6x) e (6x) 1.50 ref. 1.50 ref. d2 e2 e2 pad 1 id pad 1 index area tie bars (3) notes: 1. refer to jedec drawing mo-229. 2. this is the metallized terminal and is measured between 0.18 mm and 0.30 mm from the terminal tip. the terminal may have a straight end instead of rounded. 3. package may have exposed tie bars, ending flush with package edge. dfn millimeters sym. min. nom. max. n0. pad 8 d 2.00 bsc e 3.00 bsc d2 1.50 ? 1.75 e2 1.60 ? 1.90 a 0.70 0.75 0.80 a1 0.0 0.02 0.05 a2 ? ? 0.75 a3 0.20 ref l 0.30 0.40 0.50 e 0.50 bsc b 0.18 0.25 0.30
integrated silicon solution, inc. packaging information issi ? thin shrink small outline tssop package code: z (8 pin, 14 pin) rev b 02/01/02 tssop (z) ref. std. jedec mo-153 no. leads 8 millimeters inches symbol min max min max a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 d 2.90 3.10 0.114 0.122 e1 4.30 4.50 0.169 0.177 e 6.40 bsc 0.252 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.018 0.030 ?8 ?8 tssop (z) ref. std. jedec mo-153 no. leads 14 millimeters i nches symbol min max min max a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.10 0.193 0.201 e1 4.30 4.50 0.170 0.177 e 6.40 bsc 0.252 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.0177 0.0295 ?8 ? 8 d b e e1 a2 e c a a1 l 1 n n/2 ssi reserves the right to make changes to its products at any time without notice in order to improve design and supply the bes t possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2002, integrated silicon solution, inc.

▲Up To Search▲

Price & Availability of IS34C02B

	To Download IS34C02B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .